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Original Research Article

Year: 2015 | Month: June | Volume: 2 | Issue: 6 | Pages: 355-364

Performance Evaluation of Fault-Tolerant Routing For Network-On-Chip in Hotspot and Local Traffic

Ladan Momeni1, Arshin Rezazadeh2

1,2Faculty Member,
1Sama Technical and Vocational Training College, Islamic Azad University, Ahvaz Branch, Ahvaz, Iran
2Department of Computer Engineering, Shahid Chamran University of Ahvaz, Ahvaz, Iran

Corresponding Author: Ladan Momeni

ABSTRACT

NoC is a scalable and flexible communication medium for the design of multi-core based SoC. Communication performance of NoC depends seriously on efficient routing algorithms. Fault-tolerant routing algorithm is the ability to survive failure of individual components. We evaluated a deterministic fault-tolerant, deadlock-free routing algorithm in two-dimensional (2D) mesh based topology on Fault-Tolerant-Routing (FTR) to increase performance of the messages over the on-chip interconnection networks. The FTR algorithm is a wormhole-switched routing for 2-D mesh networks and has been used for block faults. This algorithm uses virtual channels to pass faulty regions. We have evaluated the FTR algorithm by two different traffic patterns, hotspot and local, to show message delays and performance in the network which led to an Improved-Fault-Tolerant-Algorithm (i-FTR). Moreover, to simulate FTR and i-FTR algorithms, same network conditions namely network size, message length and number of generated messages has been considered. It can be deduced from results that i-FTR performance is better compared to FTR algorithm. Furthermore, results show that the interconnection network of NoC which has been used for i-FTR can deal with higher message rates and can tolerate higher traffic loads with higher utilization.

Keywords: routing algorithm; wormhole switching; 2D-mesh interconnection networks; virtual channel.

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